Memory Senior Modeling Engineer

Company Description

The Memory Senior Modeling Engineer owns the generation, validation, and delivery of the complete set of memory views and models for Silvaco’s memory IP portfolio. As a senior technical contributor within the Memory Design team, the role ensures that every consumer of memory deliverables — Physical Design, Static Timing, DFT, and design teams — is supported by accurate, silicon-correlated, and on-time models, while continuously improving the modeling and quality-assurance methodology.

Job Description

Key Roles & Responsibilities

Memory View & Model Generation

• Develop, generate, and maintain the full set of memory views/models for the SRAM, ROM, and Register-File portfolio, ensuring correctness, completeness, and on-time delivery to consumer teams.
• Liberty Models: validate timing & power Liberty (.lib) models (NLDM/CCS) across all required PVT corners, ensuring correlation with SPICE/silicon and consistency with the memory specification.
• Memory Verilog Model: build behavioral Verilog/SystemVerilog models for memory instances and compilers, matching the functional, timing, and power-aware behavior of the hardware.

Model Verification

• Verilog Model Testing: set up and run model verification/regression environments, define test cases and equivalence checks to guarantee the Verilog models match specification and golden behavior.
• Debug model mismatches and drive root-cause analysis together with the design and CAD teams.

Design-for-Test (DFT)

• Tessent Description: create and validate memory descriptions for Siemens/Mentor Tessent to enable MBIST insertion, repair, and test of the memory blocks.
• TetraMAX: generate and debug ATPG patterns and fault coverage for memory and surrounding logic using Synopsys TetraMAX.
• FastScan: build scan/ATPG flows and analyze test coverage using Siemens/Mentor FastScan, aligning with the overall DFT strategy.

Automation & Methodology

• Automate the model-generation and QA flows (Perl/Python/TCL/Shell) and integrate them within the memory compiler / view-generation environment to improve robustness and turnaround time.
• Introduce and implement methodology improvements that enhance model quality and overall team efficiency.

Collaboration & Support

• Work in close cooperation with Memory Design, DFT, Physical Design, and STA teams to deliver on time and according to required specifications.
• Generate the required documentation, support consumers of the models, and contribute to the validation and debugging of fabricated silicon.
• Provide mentorship and technical guidance to junior modeling engineers.

Qualifications

Essential Requirements

• BS/MS in Electronics Engineering, Telecommunications, Microelectronics, Computer Engineering, Physics, or a related field.
• Minimum 4 years of hands-on experience in memory modeling, or DFT for IC/IP design.
• Liberty (.lib) timing & power model generation and validation (NLDM/CCS).
• Memory behavioral Verilog/SystemVerilog model development.
• Verilog model testing, verification, and regression methodology.
• Tessent memory description and MBIST flows.
• Synopsys TetraMAX ATPG.
• Siemens/Mentor FastScan ATPG / scan.
• Strong scripting/programming skills (Perl, Python, TCL, Shell) on Unix/Linux.
• English Language Proficiency: Fluency, written and verbal.
• Strong communication, analytical, and problem-solving skills.

Desirable Requirements

• Master's degree in Electronics / Microelectronics Engineering.
• Hands-on experience with memory compilers and view-generation flows.
• Familiarity with CCS/NLDM characterization, SPICE correlation, and standard views (LEF, GDS, CDL).
• Understanding of memory architectures (SRAM/ROM/Register File) and STA concepts.
• Experience with advanced FinFET process nodes.
• Knowledge of functional safety (ISO 26262) and quality (ISO 9001) processes.